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  <tt><a name="1"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;1&nbsp;&nbsp;</span><span class="comment">--&nbsp;VHDL&nbsp;Entity&nbsp;My_Lib.usb_rcvr.symbol<br/>
<a name="2"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;2&nbsp;&nbsp;</span></span><span class="comment">--<br/>
<a name="3"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;3&nbsp;&nbsp;</span></span><span class="comment">--&nbsp;Created:<br/>
<a name="4"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;4&nbsp;&nbsp;</span></span><span class="comment">--&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;by&nbsp;-&nbsp;mg34.bin&nbsp;(ecelinux23.ecn.purdue.edu)<br/>
<a name="5"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;5&nbsp;&nbsp;</span></span><span class="comment">--&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;at&nbsp;-&nbsp;21:25:52&nbsp;02/26/11<br/>
<a name="6"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;6&nbsp;&nbsp;</span></span><span class="comment">--<br/>
<a name="7"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;7&nbsp;&nbsp;</span></span><span class="comment">--&nbsp;Generated&nbsp;by&nbsp;Mentor&nbsp;Graphics'&nbsp;HDL&nbsp;Designer(TM)&nbsp;2009.2&nbsp;(Build&nbsp;10)<br/>
<a name="8"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;8&nbsp;&nbsp;</span></span><span class="comment">--<br/>
<a name="9"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;9&nbsp;&nbsp;</span></span><span class="keyword">LIBRARY</span>&nbsp;ieee;<br/>
<a name="10"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;10&nbsp;&nbsp;</span><span class="keyword">USE</span>&nbsp;ieee.std_logic_1164.<span class="keyword">all</span>;<br/>
<a name="11"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;11&nbsp;&nbsp;</span><span class="keyword">USE</span>&nbsp;ieee.std_logic_arith.<span class="keyword">all</span>;<br/>
<a name="12"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;12&nbsp;&nbsp;</span><br/>
<a name="13"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;13&nbsp;&nbsp;</span><span class="keyword">ENTITY</span>&nbsp;USB_RCVR&nbsp;<span class="keyword">IS</span><br/>
<a name="14"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;14&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;<span class="keyword">PORT</span>(&nbsp;<br/>
<a name="15"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;15&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keyattr">IN</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="16"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;16&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_MINUS&nbsp;&nbsp;:&nbsp;<span class="keyattr">IN</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="17"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;17&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_PLUS&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keyattr">IN</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="18"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;18&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RST_N&nbsp;&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keyattr">IN</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="19"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;19&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;R_ENABLE&nbsp;:&nbsp;<span class="keyattr">IN</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="20"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;20&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;EMPTY&nbsp;&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keyattr">OUT</span>&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="21"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;21&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;FULL&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keyattr">OUT</span>&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="22"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;22&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RCVING&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keyattr">OUT</span>&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="23"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;23&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;R_DATA&nbsp;&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keyattr">OUT</span>&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic_vector</span>&nbsp;(7&nbsp;<span class="keyword">DOWNTO</span>&nbsp;0);<br/>
<a name="24"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;24&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;R_ERROR&nbsp;&nbsp;:&nbsp;<span class="keyattr">OUT</span>&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span><br/>
<a name="25"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;25&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;);<br/>
<a name="26"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;26&nbsp;&nbsp;</span><br/>
<a name="27"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;27&nbsp;&nbsp;</span><span class="comment">--&nbsp;Declarations<br/>
<a name="28"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;28&nbsp;&nbsp;</span></span><br/>
<a name="29"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;29&nbsp;&nbsp;</span><span class="keyword">END</span>&nbsp;USB_RCVR&nbsp;;<br/>
<a name="30"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;30&nbsp;&nbsp;</span><br/>
<a name="31"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;31&nbsp;&nbsp;</span><span class="comment">--<br/>
<a name="32"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;32&nbsp;&nbsp;</span></span><span class="comment">--&nbsp;VHDL&nbsp;Architecture&nbsp;My_Lib.usb_rcvr.struct<br/>
<a name="33"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;33&nbsp;&nbsp;</span></span><span class="comment">--<br/>
<a name="34"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;34&nbsp;&nbsp;</span></span><span class="comment">--&nbsp;Created:<br/>
<a name="35"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;35&nbsp;&nbsp;</span></span><span class="comment">--&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;by&nbsp;-&nbsp;mg34.bin&nbsp;(ecelinux23.ecn.purdue.edu)<br/>
<a name="36"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;36&nbsp;&nbsp;</span></span><span class="comment">--&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;at&nbsp;-&nbsp;21:25:52&nbsp;02/26/11<br/>
<a name="37"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;37&nbsp;&nbsp;</span></span><span class="comment">--<br/>
<a name="38"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;38&nbsp;&nbsp;</span></span><span class="comment">--&nbsp;Generated&nbsp;by&nbsp;Mentor&nbsp;Graphics'&nbsp;HDL&nbsp;Designer(TM)&nbsp;2009.2&nbsp;(Build&nbsp;10)<br/>
<a name="39"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;39&nbsp;&nbsp;</span></span><span class="comment">--<br/>
<a name="40"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;40&nbsp;&nbsp;</span></span><span class="keyword">LIBRARY</span>&nbsp;ieee;<br/>
<a name="41"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;41&nbsp;&nbsp;</span><span class="keyword">USE</span>&nbsp;ieee.std_logic_1164.<span class="keyword">all</span>;<br/>
<a name="42"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;42&nbsp;&nbsp;</span><span class="keyword">USE</span>&nbsp;ieee.std_logic_arith.<span class="keyword">all</span>;<br/>
<a name="43"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;43&nbsp;&nbsp;</span><span class="keyword">LIBRARY</span>&nbsp;ECE337_IP;<br/>
<a name="44"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;44&nbsp;&nbsp;</span><span class="keyword">USE</span>&nbsp;ECE337_IP.<span class="keyword">ALL</span>;<br/>
<a name="45"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;45&nbsp;&nbsp;</span><br/>
<a name="46"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;46&nbsp;&nbsp;</span><span class="comment">--LIBRARY&nbsp;My_Lib;<br/>
<a name="47"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;47&nbsp;&nbsp;</span></span><br/>
<a name="48"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;48&nbsp;&nbsp;</span><span class="keyword">ARCHITECTURE</span>&nbsp;struct&nbsp;<span class="keyword">OF</span>&nbsp;USB_RCVR&nbsp;<span class="keyword">IS</span><br/>
<a name="49"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;49&nbsp;&nbsp;</span><br/>
<a name="50"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;50&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;<span class="comment">--&nbsp;Architecture&nbsp;declarations<br/>
<a name="51"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;51&nbsp;&nbsp;</span></span><br/>
<a name="52"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;52&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;<span class="comment">--&nbsp;Internal&nbsp;signal&nbsp;declarations<br/>
<a name="53"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;53&nbsp;&nbsp;</span></span>&nbsp;&nbsp;&nbsp;<span class="keyword">SIGNAL</span>&nbsp;D_EDGE&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="54"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;54&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;<span class="keyword">SIGNAL</span>&nbsp;D_ORIG&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="55"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;55&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;<span class="keyword">SIGNAL</span>&nbsp;EOP&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="56"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;56&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;<span class="keyword">SIGNAL</span>&nbsp;RCV_DATA&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keytype">std_logic_vector</span>(7&nbsp;<span class="keyword">DOWNTO</span>&nbsp;0);<br/>
<a name="57"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;57&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;<span class="keyword">SIGNAL</span>&nbsp;SHIFT_ENABLE&nbsp;:&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="58"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;58&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;<span class="keyword">SIGNAL</span>&nbsp;W_ENABLE&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="59"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;59&nbsp;&nbsp;</span><br/>
<a name="60"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;60&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;<span class="comment">--&nbsp;Implicit&nbsp;buffer&nbsp;signal&nbsp;declarations<br/>
<a name="61"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;61&nbsp;&nbsp;</span></span>&nbsp;&nbsp;&nbsp;<span class="keyword">SIGNAL</span>&nbsp;RCVING_internal&nbsp;:&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="62"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;62&nbsp;&nbsp;</span><br/>
<a name="63"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;63&nbsp;&nbsp;</span><br/>
<a name="64"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;64&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;<span class="comment">--&nbsp;Component&nbsp;Declarations<br/>
<a name="65"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;65&nbsp;&nbsp;</span></span>&nbsp;&nbsp;&nbsp;<span class="keyword">COMPONENT</span>&nbsp;RCV_FIFO<br/>
<a name="66"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;66&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;<span class="keyword">PORT</span>&nbsp;(<br/>
<a name="67"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;67&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keyattr">IN</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="68"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;68&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RST_N&nbsp;&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keyattr">IN</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="69"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;69&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;R_ENABLE&nbsp;:&nbsp;<span class="keyattr">IN</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="70"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;70&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;WDATA&nbsp;&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keyattr">IN</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic_vector</span>&nbsp;(7&nbsp;<span class="keyword">DOWNTO</span>&nbsp;0);<br/>
<a name="71"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;71&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;W_ENABLE&nbsp;:&nbsp;<span class="keyattr">IN</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="72"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;72&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;EMPTY&nbsp;&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keyattr">OUT</span>&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="73"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;73&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;FULL&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keyattr">OUT</span>&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="74"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;74&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;R_DATA&nbsp;&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keyattr">OUT</span>&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic_vector</span>&nbsp;(7&nbsp;<span class="keyword">DOWNTO</span>&nbsp;0)<br/>
<a name="75"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;75&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;);<br/>
<a name="76"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;76&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;<span class="keyword">END</span>&nbsp;<span class="keyword">COMPONENT</span>;<br/>
<a name="77"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;77&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;<span class="keyword">COMPONENT</span>&nbsp;DECODE<br/>
<a name="78"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;78&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;<span class="keyword">PORT</span>&nbsp;(<br/>
<a name="79"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;79&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keyattr">IN</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="80"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;80&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_PLUS&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keyattr">IN</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="81"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;81&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;EOP&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keyattr">IN</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="82"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;82&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RST_N&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keyattr">IN</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="83"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;83&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;SHIFT_ENABLE&nbsp;:&nbsp;<span class="keyattr">IN</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="84"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;84&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_ORIG&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keyattr">OUT</span>&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span><br/>
<a name="85"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;85&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;);<br/>
<a name="86"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;86&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;<span class="keyword">END</span>&nbsp;<span class="keyword">COMPONENT</span>;<br/>
<a name="87"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;87&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;<span class="keyword">COMPONENT</span>&nbsp;EDGE_DETECT<br/>
<a name="88"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;88&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;<span class="keyword">PORT</span>&nbsp;(<br/>
<a name="89"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;89&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;CLK&nbsp;&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keyattr">IN</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="90"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;90&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_PLUS&nbsp;:&nbsp;<span class="keyattr">IN</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="91"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;91&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RST_N&nbsp;&nbsp;:&nbsp;<span class="keyattr">IN</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="92"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;92&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_EDGE&nbsp;:&nbsp;<span class="keyattr">OUT</span>&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span><br/>
<a name="93"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;93&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;);<br/>
<a name="94"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;94&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;<span class="keyword">END</span>&nbsp;<span class="keyword">COMPONENT</span>;<br/>
<a name="95"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;95&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;<span class="keyword">COMPONENT</span>&nbsp;EOP_DETECT<br/>
<a name="96"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;96&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;<span class="keyword">PORT</span>&nbsp;(<br/>
<a name="97"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;97&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_MINUS&nbsp;:&nbsp;<span class="keyattr">IN</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="98"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;98&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_PLUS&nbsp;&nbsp;:&nbsp;<span class="keyattr">IN</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="99"/><span style="color:red">&nbsp;&nbsp;&nbsp;&nbsp;99&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;EOP&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keyattr">OUT</span>&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span><br/>
<a name="100"/><span style="color:red">&nbsp;&nbsp;&nbsp;100&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;);<br/>
<a name="101"/><span style="color:red">&nbsp;&nbsp;&nbsp;101&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;<span class="keyword">END</span>&nbsp;<span class="keyword">COMPONENT</span>;<br/>
<a name="102"/><span style="color:red">&nbsp;&nbsp;&nbsp;102&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;<span class="keyword">COMPONENT</span>&nbsp;RCU<br/>
<a name="103"/><span style="color:red">&nbsp;&nbsp;&nbsp;103&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;<span class="keyword">PORT</span>&nbsp;(<br/>
<a name="104"/><span style="color:red">&nbsp;&nbsp;&nbsp;104&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keyattr">IN</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="105"/><span style="color:red">&nbsp;&nbsp;&nbsp;105&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_EDGE&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keyattr">IN</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="106"/><span style="color:red">&nbsp;&nbsp;&nbsp;106&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;EOP&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keyattr">IN</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="107"/><span style="color:red">&nbsp;&nbsp;&nbsp;107&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RCV_DATA&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keyattr">IN</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic_vector</span>&nbsp;(7&nbsp;<span class="keyword">DOWNTO</span>&nbsp;0);<br/>
<a name="108"/><span style="color:red">&nbsp;&nbsp;&nbsp;108&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RST_N&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keyattr">IN</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="109"/><span style="color:red">&nbsp;&nbsp;&nbsp;109&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;SHIFT_ENABLE&nbsp;:&nbsp;<span class="keyattr">IN</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="110"/><span style="color:red">&nbsp;&nbsp;&nbsp;110&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RCVING&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keyattr">OUT</span>&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="111"/><span style="color:red">&nbsp;&nbsp;&nbsp;111&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;R_ERROR&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keyattr">OUT</span>&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="112"/><span style="color:red">&nbsp;&nbsp;&nbsp;112&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;W_ENABLE&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keyattr">OUT</span>&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span><br/>
<a name="113"/><span style="color:red">&nbsp;&nbsp;&nbsp;113&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;);<br/>
<a name="114"/><span style="color:red">&nbsp;&nbsp;&nbsp;114&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;<span class="keyword">END</span>&nbsp;<span class="keyword">COMPONENT</span>;<br/>
<a name="115"/><span style="color:red">&nbsp;&nbsp;&nbsp;115&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;<span class="keyword">COMPONENT</span>&nbsp;SHIFT_REG<br/>
<a name="116"/><span style="color:red">&nbsp;&nbsp;&nbsp;116&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;<span class="keyword">PORT</span>&nbsp;(<br/>
<a name="117"/><span style="color:red">&nbsp;&nbsp;&nbsp;117&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keyattr">IN</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="118"/><span style="color:red">&nbsp;&nbsp;&nbsp;118&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_ORIG&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keyattr">IN</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="119"/><span style="color:red">&nbsp;&nbsp;&nbsp;119&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RST_N&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keyattr">IN</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="120"/><span style="color:red">&nbsp;&nbsp;&nbsp;120&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;SHIFT_ENABLE&nbsp;:&nbsp;<span class="keyattr">IN</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="121"/><span style="color:red">&nbsp;&nbsp;&nbsp;121&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RCV_DATA&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keyattr">OUT</span>&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic_vector</span>&nbsp;(7&nbsp;<span class="keyword">DOWNTO</span>&nbsp;0)<br/>
<a name="122"/><span style="color:red">&nbsp;&nbsp;&nbsp;122&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;);<br/>
<a name="123"/><span style="color:red">&nbsp;&nbsp;&nbsp;123&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;<span class="keyword">END</span>&nbsp;<span class="keyword">COMPONENT</span>;<br/>
<a name="124"/><span style="color:red">&nbsp;&nbsp;&nbsp;124&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;<span class="keyword">COMPONENT</span>&nbsp;TIMER<br/>
<a name="125"/><span style="color:red">&nbsp;&nbsp;&nbsp;125&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;<span class="keyword">PORT</span>&nbsp;(<br/>
<a name="126"/><span style="color:red">&nbsp;&nbsp;&nbsp;126&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keyattr">IN</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="127"/><span style="color:red">&nbsp;&nbsp;&nbsp;127&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_EDGE&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keyattr">IN</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="128"/><span style="color:red">&nbsp;&nbsp;&nbsp;128&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RCVING&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keyattr">IN</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="129"/><span style="color:red">&nbsp;&nbsp;&nbsp;129&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RST_N&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;:&nbsp;<span class="keyattr">IN</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span>;<br/>
<a name="130"/><span style="color:red">&nbsp;&nbsp;&nbsp;130&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;SHIFT_ENABLE&nbsp;:&nbsp;<span class="keyattr">OUT</span>&nbsp;&nbsp;&nbsp;&nbsp;<span class="keytype">std_logic</span><br/>
<a name="131"/><span style="color:red">&nbsp;&nbsp;&nbsp;131&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;);<br/>
<a name="132"/><span style="color:red">&nbsp;&nbsp;&nbsp;132&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;<span class="keyword">END</span>&nbsp;<span class="keyword">COMPONENT</span>;<br/>
<a name="133"/><span style="color:red">&nbsp;&nbsp;&nbsp;133&nbsp;&nbsp;</span><br/>
<a name="134"/><span style="color:red">&nbsp;&nbsp;&nbsp;134&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;<span class="comment">--&nbsp;Optional&nbsp;embedded&nbsp;configurations<br/>
<a name="135"/><span style="color:red">&nbsp;&nbsp;&nbsp;135&nbsp;&nbsp;</span></span>&nbsp;&nbsp;&nbsp;<span class="comment">--&nbsp;pragma&nbsp;synthesis_off<br/>
<a name="136"/><span style="color:red">&nbsp;&nbsp;&nbsp;136&nbsp;&nbsp;</span></span>&nbsp;&nbsp;&nbsp;<span class="comment">--FOR&nbsp;ALL&nbsp;:&nbsp;RCV_FIFO&nbsp;USE&nbsp;ENTITY&nbsp;My_Lib.RCV_FIFO;<br/>
<a name="137"/><span style="color:red">&nbsp;&nbsp;&nbsp;137&nbsp;&nbsp;</span></span>&nbsp;&nbsp;&nbsp;<span class="comment">--FOR&nbsp;ALL&nbsp;:&nbsp;decode&nbsp;USE&nbsp;ENTITY&nbsp;My_Lib.decode;<br/>
<a name="138"/><span style="color:red">&nbsp;&nbsp;&nbsp;138&nbsp;&nbsp;</span></span>&nbsp;&nbsp;&nbsp;<span class="comment">--FOR&nbsp;ALL&nbsp;:&nbsp;edge_detect&nbsp;USE&nbsp;ENTITY&nbsp;My_Lib.edge_detect;<br/>
<a name="139"/><span style="color:red">&nbsp;&nbsp;&nbsp;139&nbsp;&nbsp;</span></span>&nbsp;&nbsp;&nbsp;<span class="comment">--FOR&nbsp;ALL&nbsp;:&nbsp;eop_detect&nbsp;USE&nbsp;ENTITY&nbsp;My_Lib.eop_detect;<br/>
<a name="140"/><span style="color:red">&nbsp;&nbsp;&nbsp;140&nbsp;&nbsp;</span></span>&nbsp;&nbsp;&nbsp;<span class="comment">--FOR&nbsp;ALL&nbsp;:&nbsp;rcu&nbsp;USE&nbsp;ENTITY&nbsp;My_Lib.rcu;<br/>
<a name="141"/><span style="color:red">&nbsp;&nbsp;&nbsp;141&nbsp;&nbsp;</span></span>&nbsp;&nbsp;&nbsp;<span class="comment">--FOR&nbsp;ALL&nbsp;:&nbsp;shift_reg&nbsp;USE&nbsp;ENTITY&nbsp;My_Lib.shift_reg;<br/>
<a name="142"/><span style="color:red">&nbsp;&nbsp;&nbsp;142&nbsp;&nbsp;</span></span>&nbsp;&nbsp;&nbsp;<span class="comment">--FOR&nbsp;ALL&nbsp;:&nbsp;timer&nbsp;USE&nbsp;ENTITY&nbsp;My_Lib.timer;<br/>
<a name="143"/><span style="color:red">&nbsp;&nbsp;&nbsp;143&nbsp;&nbsp;</span></span>&nbsp;&nbsp;&nbsp;<span class="comment">--&nbsp;pragma&nbsp;synthesis_on<br/>
<a name="144"/><span style="color:red">&nbsp;&nbsp;&nbsp;144&nbsp;&nbsp;</span></span><br/>
<a name="145"/><span style="color:red">&nbsp;&nbsp;&nbsp;145&nbsp;&nbsp;</span><br/>
<a name="146"/><span style="color:red">&nbsp;&nbsp;&nbsp;146&nbsp;&nbsp;</span><span class="keyword">BEGIN</span><br/>
<a name="147"/><span style="color:red">&nbsp;&nbsp;&nbsp;147&nbsp;&nbsp;</span><br/>
<a name="148"/><span style="color:red">&nbsp;&nbsp;&nbsp;148&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;<span class="comment">--&nbsp;Instance&nbsp;port&nbsp;mappings.<br/>
<a name="149"/><span style="color:red">&nbsp;&nbsp;&nbsp;149&nbsp;&nbsp;</span></span>&nbsp;&nbsp;&nbsp;U_3&nbsp;:&nbsp;RCV_FIFO<br/>
<a name="150"/><span style="color:red">&nbsp;&nbsp;&nbsp;150&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keyword">PORT</span>&nbsp;<span class="keyword">MAP</span>&nbsp;(<br/>
<a name="151"/><span style="color:red">&nbsp;&nbsp;&nbsp;151&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=&gt;&nbsp;CLK,<br/>
<a name="152"/><span style="color:red">&nbsp;&nbsp;&nbsp;152&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RST_N&nbsp;&nbsp;&nbsp;&nbsp;=&gt;&nbsp;RST_N,<br/>
<a name="153"/><span style="color:red">&nbsp;&nbsp;&nbsp;153&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;R_ENABLE&nbsp;=&gt;&nbsp;R_ENABLE,<br/>
<a name="154"/><span style="color:red">&nbsp;&nbsp;&nbsp;154&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;W_ENABLE&nbsp;=&gt;&nbsp;W_ENABLE,<br/>
<a name="155"/><span style="color:red">&nbsp;&nbsp;&nbsp;155&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;WDATA&nbsp;&nbsp;&nbsp;&nbsp;=&gt;&nbsp;RCV_DATA,<br/>
<a name="156"/><span style="color:red">&nbsp;&nbsp;&nbsp;156&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;R_DATA&nbsp;&nbsp;&nbsp;&nbsp;=&gt;&nbsp;R_DATA,<br/>
<a name="157"/><span style="color:red">&nbsp;&nbsp;&nbsp;157&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;EMPTY&nbsp;&nbsp;&nbsp;&nbsp;=&gt;&nbsp;EMPTY,<br/>
<a name="158"/><span style="color:red">&nbsp;&nbsp;&nbsp;158&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;FULL&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=&gt;&nbsp;FULL<br/>
<a name="159"/><span style="color:red">&nbsp;&nbsp;&nbsp;159&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;);<br/>
<a name="160"/><span style="color:red">&nbsp;&nbsp;&nbsp;160&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;U_6&nbsp;:&nbsp;DECODE<br/>
<a name="161"/><span style="color:red">&nbsp;&nbsp;&nbsp;161&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keyword">PORT</span>&nbsp;<span class="keyword">MAP</span>&nbsp;(<br/>
<a name="162"/><span style="color:red">&nbsp;&nbsp;&nbsp;162&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=&gt;&nbsp;CLK,<br/>
<a name="163"/><span style="color:red">&nbsp;&nbsp;&nbsp;163&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RST_N&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=&gt;&nbsp;RST_N,<br/>
<a name="164"/><span style="color:red">&nbsp;&nbsp;&nbsp;164&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_PLUS&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=&gt;&nbsp;D_PLUS,<br/>
<a name="165"/><span style="color:red">&nbsp;&nbsp;&nbsp;165&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;SHIFT_ENABLE&nbsp;=&gt;&nbsp;SHIFT_ENABLE,<br/>
<a name="166"/><span style="color:red">&nbsp;&nbsp;&nbsp;166&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;EOP&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=&gt;&nbsp;EOP,<br/>
<a name="167"/><span style="color:red">&nbsp;&nbsp;&nbsp;167&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_ORIG&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=&gt;&nbsp;D_ORIG<br/>
<a name="168"/><span style="color:red">&nbsp;&nbsp;&nbsp;168&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;);<br/>
<a name="169"/><span style="color:red">&nbsp;&nbsp;&nbsp;169&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;U_5&nbsp;:&nbsp;EDGE_DETECT<br/>
<a name="170"/><span style="color:red">&nbsp;&nbsp;&nbsp;170&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keyword">PORT</span>&nbsp;<span class="keyword">MAP</span>&nbsp;(<br/>
<a name="171"/><span style="color:red">&nbsp;&nbsp;&nbsp;171&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;CLK&nbsp;&nbsp;&nbsp;&nbsp;=&gt;&nbsp;CLK,<br/>
<a name="172"/><span style="color:red">&nbsp;&nbsp;&nbsp;172&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RST_N&nbsp;&nbsp;=&gt;&nbsp;RST_N,<br/>
<a name="173"/><span style="color:red">&nbsp;&nbsp;&nbsp;173&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_PLUS&nbsp;=&gt;&nbsp;D_PLUS,<br/>
<a name="174"/><span style="color:red">&nbsp;&nbsp;&nbsp;174&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_EDGE&nbsp;=&gt;&nbsp;D_EDGE<br/>
<a name="175"/><span style="color:red">&nbsp;&nbsp;&nbsp;175&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;);<br/>
<a name="176"/><span style="color:red">&nbsp;&nbsp;&nbsp;176&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;U_4&nbsp;:&nbsp;EOP_DETECT<br/>
<a name="177"/><span style="color:red">&nbsp;&nbsp;&nbsp;177&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keyword">PORT</span>&nbsp;<span class="keyword">MAP</span>&nbsp;(<br/>
<a name="178"/><span style="color:red">&nbsp;&nbsp;&nbsp;178&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_PLUS&nbsp;&nbsp;=&gt;&nbsp;D_PLUS,<br/>
<a name="179"/><span style="color:red">&nbsp;&nbsp;&nbsp;179&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_MINUS&nbsp;=&gt;&nbsp;D_MINUS,<br/>
<a name="180"/><span style="color:red">&nbsp;&nbsp;&nbsp;180&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;EOP&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=&gt;&nbsp;EOP<br/>
<a name="181"/><span style="color:red">&nbsp;&nbsp;&nbsp;181&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;);<br/>
<a name="182"/><span style="color:red">&nbsp;&nbsp;&nbsp;182&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;U_2&nbsp;:&nbsp;RCU<br/>
<a name="183"/><span style="color:red">&nbsp;&nbsp;&nbsp;183&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keyword">PORT</span>&nbsp;<span class="keyword">MAP</span>&nbsp;(<br/>
<a name="184"/><span style="color:red">&nbsp;&nbsp;&nbsp;184&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=&gt;&nbsp;CLK,<br/>
<a name="185"/><span style="color:red">&nbsp;&nbsp;&nbsp;185&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RST_N&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=&gt;&nbsp;RST_N,<br/>
<a name="186"/><span style="color:red">&nbsp;&nbsp;&nbsp;186&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_EDGE&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=&gt;&nbsp;D_EDGE,<br/>
<a name="187"/><span style="color:red">&nbsp;&nbsp;&nbsp;187&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;EOP&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=&gt;&nbsp;EOP,<br/>
<a name="188"/><span style="color:red">&nbsp;&nbsp;&nbsp;188&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;SHIFT_ENABLE&nbsp;=&gt;&nbsp;SHIFT_ENABLE,<br/>
<a name="189"/><span style="color:red">&nbsp;&nbsp;&nbsp;189&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RCV_DATA&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=&gt;&nbsp;RCV_DATA,<br/>
<a name="190"/><span style="color:red">&nbsp;&nbsp;&nbsp;190&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RCVING&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=&gt;&nbsp;RCVING_internal,<br/>
<a name="191"/><span style="color:red">&nbsp;&nbsp;&nbsp;191&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;W_ENABLE&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=&gt;&nbsp;W_ENABLE,<br/>
<a name="192"/><span style="color:red">&nbsp;&nbsp;&nbsp;192&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;R_ERROR&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=&gt;&nbsp;R_ERROR<br/>
<a name="193"/><span style="color:red">&nbsp;&nbsp;&nbsp;193&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;);<br/>
<a name="194"/><span style="color:red">&nbsp;&nbsp;&nbsp;194&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;U_1&nbsp;:&nbsp;SHIFT_REG<br/>
<a name="195"/><span style="color:red">&nbsp;&nbsp;&nbsp;195&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keyword">PORT</span>&nbsp;<span class="keyword">MAP</span>&nbsp;(<br/>
<a name="196"/><span style="color:red">&nbsp;&nbsp;&nbsp;196&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=&gt;&nbsp;CLK,<br/>
<a name="197"/><span style="color:red">&nbsp;&nbsp;&nbsp;197&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RST_N&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=&gt;&nbsp;RST_N,<br/>
<a name="198"/><span style="color:red">&nbsp;&nbsp;&nbsp;198&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;SHIFT_ENABLE&nbsp;=&gt;&nbsp;SHIFT_ENABLE,<br/>
<a name="199"/><span style="color:red">&nbsp;&nbsp;&nbsp;199&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_ORIG&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=&gt;&nbsp;D_ORIG,<br/>
<a name="200"/><span style="color:red">&nbsp;&nbsp;&nbsp;200&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RCV_DATA&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=&gt;&nbsp;RCV_DATA<br/>
<a name="201"/><span style="color:red">&nbsp;&nbsp;&nbsp;201&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;);<br/>
<a name="202"/><span style="color:red">&nbsp;&nbsp;&nbsp;202&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;U_0&nbsp;:&nbsp;TIMER<br/>
<a name="203"/><span style="color:red">&nbsp;&nbsp;&nbsp;203&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<span class="keyword">PORT</span>&nbsp;<span class="keyword">MAP</span>&nbsp;(<br/>
<a name="204"/><span style="color:red">&nbsp;&nbsp;&nbsp;204&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=&gt;&nbsp;CLK,<br/>
<a name="205"/><span style="color:red">&nbsp;&nbsp;&nbsp;205&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RST_N&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=&gt;&nbsp;RST_N,<br/>
<a name="206"/><span style="color:red">&nbsp;&nbsp;&nbsp;206&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;D_EDGE&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=&gt;&nbsp;D_EDGE,<br/>
<a name="207"/><span style="color:red">&nbsp;&nbsp;&nbsp;207&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RCVING&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=&gt;&nbsp;RCVING_internal,<br/>
<a name="208"/><span style="color:red">&nbsp;&nbsp;&nbsp;208&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;SHIFT_ENABLE&nbsp;=&gt;&nbsp;SHIFT_ENABLE<br/>
<a name="209"/><span style="color:red">&nbsp;&nbsp;&nbsp;209&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;);<br/>
<a name="210"/><span style="color:red">&nbsp;&nbsp;&nbsp;210&nbsp;&nbsp;</span><br/>
<a name="211"/><span style="color:red">&nbsp;&nbsp;&nbsp;211&nbsp;&nbsp;</span>&nbsp;&nbsp;&nbsp;<span class="comment">--&nbsp;Implicit&nbsp;buffered&nbsp;output&nbsp;assignments<br/>
<a name="212"/><span style="color:red">&nbsp;&nbsp;&nbsp;212&nbsp;&nbsp;</span></span>&nbsp;&nbsp;&nbsp;RCVING&nbsp;&lt;=&nbsp;RCVING_internal;<br/>
<a name="213"/><span style="color:red">&nbsp;&nbsp;&nbsp;213&nbsp;&nbsp;</span><br/>
<a name="214"/><span style="color:red">&nbsp;&nbsp;&nbsp;214&nbsp;&nbsp;</span><span class="keyword">END</span>&nbsp;struct;<br/>
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